Programmable logic devices (PLDs) are a well-known type of integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
ICs use various sorts of devices to create logic circuits. Many types of ICs use complementary metal-oxide-semiconductor (“CMOS”) logic circuits. CMOS logic circuits use CMOS cells that have a first-conductivity-type metal-oxide-semiconductor (“MOS”) transistor (e.g., a p-type MOS (“PMOS”) transistor) paired with a second-conductivity-type MOS transistor (e.g., an n-type MOS (“NMOS”) transistor). CMOS cells can hold a logic state while drawing only very small amounts of current.
It is generally desirable that MOS transistors, whether used in a CMOS cell or used individually, provide good conductivity between the source and the drain of the MOS transistor when operating voltage is applied to the gate of the MOS transistor. In other words, it is desirable that current flows through the channel between the source and the drain when the MOS transistor is turned on.
The amount of current flowing through the channel of an MOS transistor is proportional to the mobility of charge carriers in the channel. Increasing the mobility of the charge carriers increases the amount of current that flows at a given gate voltage. Higher current flow through the channel allows the MOS transistor to operate faster. One of the ways to increase carrier mobility in the channel of a MOS transistor is to produce strain in the channel.
There are several ways to create strain in the channel region. One approach is to deposit stressed layers over a MOS transistor. Another approach is to modify existing structures, such as by implanting ions into the drain and source regions. Yet another approach is to grow stressed material in a recess of the source and/or drain region of a MOS transistor.
FIG. 1A is a simplified cross section of a prior art CMOS cell 100. The CMOS cell includes an NMOS transistor and a PMOS transistor fabricated on a silicon wafer substrate 101. The NMOS transistor is separated from the PMOS transistor by a dielectric-filled isolation trench 103. A tensile silicon nitride layer 102 overlies the source 104, gate 106 and drain 108 regions of the NMOS transistor, and a compressive silicon nitride layer 112 overlies the source 114, gate 116, and drain 118 regions of the PMOS transistor. The tensile silicon nitride layer 102 produces tensile strain in the channel 110 of the NMOS transistor, and the compressive silicon nitride layer 112 produces compressive strain in the channel 120 of the PMOS transistor, each of which enhances charge carrier mobility. The tensile silicon nitride layer is deposited and selectively etched, and then the compressive silicon nitride layer is deposited and selectively etched, or vice versa.
FIG. 1B is a simplified cross section of a prior art CMOS cell 130 having a tensile silicon nitride layer 132 formed over both the NMOS transistor and the PMOS transistor. The PMOS transistor includes silicon-germanium (SiGe) refilled source and drain 134, 136 formed by selective epitaxy in cavities etched into the source and drain regions of the PMOS transistor. The SiGe plugs provide compressive stress; however, the compressive strain provided to the channel 138 is undesirably reduced by the overlying tensile silicon nitride layer 132.
FIG. 1C is a simplified cross section of a prior art CMOS cell 150 having a tensile silicon nitride layer 152 formed over both the NMOS transistor and a PMOS transistor, and having extended SiGe plugs 154, 156. The extended SiGe plugs 154, 156 are epitaxially grown to extend above the original surface 157 of the silicon wafer substrate 101. This provides additional compressive stress and also moves the tensile silicon nitride layer 152 further from the channel 158 of the PMOS transistor, thus avoiding some of the reduction of strain that occurs in the PMOS transistor of FIG. 1B.
However, growing SiGe by selective epitaxy requires process steps outside of normal CMOS fabrication techniques, which complicates fabrication. Furthermore, growing the epitaxial SiGe typically involves removing a CMOS wafer from the process stream, which increases the possibility of contamination and defect formation. While the silicon nitride films of FIG. 1A provide some level of tensile and compressive strain, higher strains are desirable to further improve carrier mobility.